The present invention relates to a method for forming a side contact in a semiconductor device, and more particularly, to the method for forming a side contact in a semiconductor device having reduced contact resistance by exchange of the natural oxide film on the side contact with a conductive material.
In general, as supply voltages for semiconductor memory devices decrease with reductions in the devices' dimensions, memory cell stability during read/write operations has become an increasingly important issue in the development of high capacity, semiconductor memory devices, such as the static random access memory (SRAM). For 16 Mb SRAMs, a symmetrically split word line cell has been proposed which prevents degradation of cell stability. In the split word line cell structure, each cell has two word lines. Thus, a very tight bit line pitch is required. This creates problems in reducing the cell size and in obtaining higher speed operation. In order to overcome these problems, a center word line cell structure having the word lines located in the center of each cell has been proposed. See, for example, IEDM '93 at pages 817 through 820.
FIGS. 1-3 show the various layouts adapted for use with a conventional center word line cell. More specifically, FIG. 1 is the layout of a bulk transistor. FIGS. 2 and 3 are respectively layouts of a thin-film transistor (TFT), and a capacitor. Within these FIGS., reference numeral 1 denotes an active layer; 3, a first polysilicon layer for a word line and driving transistor; 5, a TFT gate electrode; 7, a TFT channel; 9, a self-aligned contact; 11, a capacitor electrode; 13, a ground plate; and 15, a side contact.
The above center word line cell has a symmetrical layout with word line (first polysilicon layer) 3 being located in the center of the cell. This cell structure saves space when compared to the additional word line used in the split word line cell. As such, cell size can be reduced while preserving sufficient space for the required bit-line pitch.
FIG. 4 is a cross-sectional view of the above center word line cell. Basically, the center word line cell is made of five layers of polysilicon placed over impurity regions 18 formed in a substrate 17. The five polysilicon layers consist of first polysilicon patterns 19a, 19b and 19c forming an access transistor, and a drive transistor; a second polysilicon layer 21 used as a load TFT gate electrode on the center of the cell; a third polysilicon layer 23 as a TFT channel; a fourth polysilicon layer 25 used as a capacitor electrode; and, a fifth polysilicon layer 27 used as a ground plate. Reference numeral 31 donates a bit line.
The center word line cell uses a side contact, shown in area "AA" of FIG. 4. First polysilicon plug 29a is commonly connected to first, second, third and fourth polysilicon layers 19a, 21, 23 and 25. In particular, first polysilicon plug 29a is connected at its side to second and third polysilicon layers 21 and 23. Second polysilicon plug 29b is also connected between ground plate 27 and impurity region 18 in substrate 17.
The noted side contact will now be explained in greater detail with reference to FIG. 5 which is a cross-sectional view of a conventional side contact. Here, an impurity region 42 has been selectively formed in substrate 41. First insulating layer 43, first conductive layer (polysilicon layer) 45, and second insulating layer 47 are each sequentially formed over substrate 41 with a contact hole through each layer to expose impurity region 42. Second conductive layer (polysilicon plug) 49 fills the contact hole to form the side contact structure.
In the foregoing structure of the conventional side contact, natural oxide layer 44 forms on the side edge of first conductive layer 45. The formation of natural oxide layer 44 increases the contact resistance between polysilicon plug 49 and first conductive layer 45. In extreme cases where contact resistance increases to unacceptable levels, electrical connection may ultimately prove impossible.